Attend our presentation at CDNLive, the Cadence Yearly User Group meeting in Munich on May 21

Posted by marleen on January 31, 2014

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Abstract:
Methods2Business wants to be a totally new IP design company where young engineering talent develops the most complex IPs needed in today’s embedded systems by using the newest system level design solutions.

In earlier presentations we addressed the problem of the growing amount of software in today’s embedded systems by combining virtual platforms with model driven software development aiming for a formally proven design flow starting from an unambiguous HW/SW contract. We demonstrated that it is possible to reflect the assumptions made in the contract in the SystemC models generated by the Cadence® Virtual System Platform solution and even formally prove them on the final RTL using Cadence® Incisive Formal Verifier (IFV) solution.

This year’s presentation will address the problem that IC design productivity has leveled off due to the fact that RTL-based design and verification methodologies have reached their limits and only a next step in design abstraction can provide the necessary increase in design productivity.  

 

Methods2Business realized a giant leap in design productivity by using the Cadence® C-to-Silicon High Level Synthesis solution to design their Wi-Fi™ 802.11n MAC core. The company worked out a design methodology that makes it possible to use the same SystemC model for High Level Synthesis as well as for early software validation in the virtual platform.

 

Thanks to the usage of C-to-Silicon, the IP core is much better verified, easier to re-use and highly customizable in terms of functionality, performance and resources which allows Methods2Business to sell their core for a broader range of applications.

 

Proposed Abstract Takeaways

High Level Synthesis using C-to-Silicon compiler creates a giant leap in design productivity and makes designs more re-usable, better verifiable and easier to customize; all this with much less effort and resources than currently needed for IP development.

 

IPs like the MAC 802.11n are complex hardware and software systems which require in-depth verification. Having the SW up and running early in the design cycle with full debug visibility on a high level model which later on becomes the golden reference model for the design, enables much more efficient verification of the hardware/software combination leading to a more optimized design and a shorter design cycle.

 

The Cadence Virtual platform of the Xilinx® ZYNQ™ 7000 EPP platform is an easy to use development platform with excellent debug capabilities.